LVCMOS Clock Generator

The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency. The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 ? transmission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.

Features

  • Low based low-voltage clock generator
  • Supports zero-delay operation
  • 3.3 V power supply
  • Generates clock signals up to 250 MHz
  • Maximum output skew of 120 ps
  • Differential LVPECL reference clock input
  • External PLL feedback
  • Drives up to 20 clock lines
  • 32-lead LQFP packaging
  • 32-lead Pb-free Package Available
  • Pin and function compatible to the MPC958

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MPC9658AC Obsolete PRG32 TQFP 32 C Yes Tray Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
MPC9658 Datasheet Datasheet PDF 392 KB Feb 24, 2013
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB May 7, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB May 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 4, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 11, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 14, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PDN# : N-12-48 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB Dec 20, 2012
PDN# N-10-04 Product Discontinuation Notice PDF 100 KB Dec 9, 2010
PCN# : A-0610-02 ASAT China as Alternate Facility for CABGA/CVBGA/FPBGA/TQFP/PQFP Product Change Notice PDF 252 KB Oct 18, 2006

Software & Tools

Title Other Languages Type Format File Size Date
MPC9658 IBIS Model Model - IBIS ZIP 18 KB Oct 14, 2007