3.3V 1:12 LVCMOS PLL Clock Generator

NOTICE - The following device(s) are recommended alternatives:

The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of theMPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. Thereference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to matchthe VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs aswell as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of thefeedback frequency is independent of the output frequencies. This allows for very flexible programming of the input referenceversus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition,the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinaryfactor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of systembaseline timing signals.The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternativeLVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configurationfor test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristicsdo not apply.The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of theMPC9773. The MPC9773 has an internal power-on reset.The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) acceptLVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 ? transmissionLVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 ? transmissionlines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices aneffective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.

Features

  • 1:12 PLL based low-voltage clock generator
  • 3.3 V power supply
  • Internal power-on reset
  • Generates clock signals up to 242.5 MHz
  • Maximum output skew of 250 ps
  • Differential PECL reference clock input
  • Two LVCMOS PLL reference clock inputs
  • External PLL feedback supports zero-delay capability
  • Various feedback and output dividers (refer to Application Section)
  • Supports up to three individual generated output clock frequencies
  • Synchronous output clock stop circuitry for each individual output for powerdown support
  • Drives up to 24 clock lines
  • Ambient temperature range -40°C to +85°C
  • Pin and function compatible to the MPC973
  • 52-lead Pb-free package available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MPC9773AE Obsolete PPG52 TQFP 52 C Yes Tray Availability
MPC9773AER2 Obsolete PPG52 TQFP 52 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
MPC9773 Datasheet Datasheet PDF 258 KB Mar 15, 2016
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB May 7, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB May 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 4, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 11, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 14, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
PCNs & PDNs
PDN#: N-16-02 PRODUCT DISCONTINUANCE NOTICE ON SELECT DEVICES Product Discontinuation Notice PDF 161 KB Mar 6, 2016
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 21, 2015
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 20, 2015
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PDN# : N-12-48 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB Dec 20, 2012

Software & Tools

Title Other Languages Type Format File Size Date
MPC9773 Datasheet Model - IBIS ZIP 10 KB Dec 11, 2007