NOTICE - The following device(s) are recommended alternatives:
74SSTUBF32866B - 25-Bit Configurable Registered Buffer for DDR2
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.
- 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSR and RESET inputs
- Low voltage operation VDD = 1.7V to 1.9V