28-Bit Configurable Registered Buffer for DDR2

NOTICE - The following device(s) are recommended alternatives:

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.

Features

  • 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation
  • Inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS
  • Outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
SSTUAF32868BHLF Obsolete BKG176 CABGA 176 C Yes Tray Availability
SSTUAF32868BHLFT Obsolete BKG176 CABGA 176 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
SSTUAF32868B Datasheet Datasheet PDF 551 KB Sep 3, 2007