The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9955 has sixteen programmable skew outputs in eight banks of 2. The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK is high when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative edge of REF. The IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.

Features

  • Ref input is 5V tolerant
  • 8 pairs of programmable skew outputs
  • Two separate A and B banks for individual control
  • Low skew: 185ps same pair, 250ps same bank, 350ps both banks
  • Selectable positive or negative edge synchronization on each bank: excellent for DSP applications
  • Synchronous output enable on each bank
  • Input frequency: 2MHz to 200MHz
  • Output frequency: 6MHz to 200MHz
  • 3-level inputs for skew and PLL range control
  • 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
  • PLL bypass for DC testing
  • External feedback, internal loop filter
  • 12mA balanced drive outputs
  • Low Jitter: <125ps cycle-to-cycle
  • Power-down mode on each bank
  • Lock indicator on each bank
  • Available in BGA package
  • Not Recommended for New Design

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5V9955BFGI Obsolete BFG96 CABGA 96 I Yes Tray
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 128 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
PCNs & PDNs
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB