Renesas PLL clock generators synthesize high-quality clock output frequencies within strict tolerances to the application they are sourcing. Using a low-cost, fundamental-mode quartz crystal, the Renesas PLL clock generators support many wide-frequency, low-jitter clocking applications with different single-ended or differential output signalling levels such as LVCMOS, LVPECL, LVDS, HCSL, HSTL.
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Industry-leading PLL Clock Generators (Clock PLL)
Renesas general purpose clock generators are phase-locked loop (PLL-based) Clock generators that can synthesize different output frequencies from a common reference input frequency. These innovative PLL-based products can generate several output frequencies that can readily be selected with very high resolution (very small frequency steps). The clock PLLs use a simple, low-cost, fundamental-mode quartz crystal or reference clock as the frequency reference, from which they generate very high frequency, low-jitter outputs with single-ended or differential signalling levels such as LVCMOS, LVPECL, LVDS, HCSL, HSTL, etc.
Renesas clock synthesizers include oscillator circuitry, which enables this device to be driven with a low-cost crystal instead of a more expensive crystal oscillator. This circuitry provides low jitter performance with a wide frequency range. Using silicon device integration techniques, these devices offer more functionality than fixed frequency crystal oscillators. In many cases, with the integration of the clock PLL, frequency multiplier, frequency divider and fanout buffer, these devices allow users to generate the whole clock tree on a single device.
Renesas' broad selection of multi-output devices can provide multiple copies of some frequencies to drive multiple loads as needed. Some PLL clock generators provide a programmable-skew feature allowing the user to adjust the timing of individual outputs. This provides flexibility for last- minute clock skew management in the system. Furthermore, some PLL clock generators feature an external feedback path, permitting precise control of clock signal timing to loads.
Frequency Multiplier Functionality
Many applications require high-frequency clock signal with low phase noise. One method to achieve this is to connect a high-quality lower- frequency signal to a frequency multiplier, generating the required high frequency at the output. Frequency multipliers use phase-locked loops and are generally regarded as a good way to generate low-noise, high-frequency clock signals. Although, even if a frequency multiplier device itself introduces no phase noise of its own, the process of frequency multiplication will inevitably add some phase noise. With that said, multiplying a very stable low-frequency reference signal can still produce signals with better quality than producing them directly. For this reason, many of the Renesas PLL clock generators allow for frequency translation - either multiplication (frequency multiplier) or division (frequency divider). The wide selection of PLL clock generators with innovative clock PLL technology helps meet the needs of virtually any application.
About PLL Clock Generators and Phase-locked Loops (PLLs)
PLL clock generators are silicon IC with phase-locked loops that can generate different high-frequency outputs from a low frequency input reference. They are sometimes called phase-locked loops, or just PLLs, although the phase-locked loop is just one piece of circuitry that the device uses. Phase-locked loops contain a voltage- or current-driven oscillator that is constantly adjusted to match (lock on to) the frequency of the input signal. In addition to locking on to a particular frequency, a phase-locked loop is generally used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.