The core functionality of the 82V3255 T0 DPLL consists of two state machines; an input clock qualification machine to assess the suitability of the input signals on all input clock ports to serve as references to the second state machine, the core DPLL that generates the DPLL output clocks. The T0 DPLL supports three primary operating states (modes) shown in red: Free-Run, Locked and Holdover. Also shown are the four secondary, temporary operating states (modes): Temp-Locked, Pre-Locked, Pre-Locked2 and Lost-Phase. Transitions between these states are caused by changes in either the:
1. Input reference selection made either automatically by the input clock state machine or manually by the user (no clocks available, clocks switched, disqualified or newly qualified).
2. Instantaneous phase of the input reference.
3. Phase relationship between the selected input reference and the DPLL output clock.
4. Output clock frequency ppm error.
Refer to application note AN-850 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.


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Application Notes & White Papers
AN-850 82V3255 T0 DPLL State Transition Diagram Application Note PDF 141 KB