NOTICE - The following device(s) are recommended alternatives:
The ADC1215S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1215S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode. It supports the LVDS DDR output standard. An integrated SPI allows the user to easily configure the ADC. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more. The integrated input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range.

特長

  • 12-bit pipelined ADC core
  • Clock input divider by 2 for less jitter contribution
  • CMOS or LVDS DDR digital outputs
  • Duty cycle stabilizer
  • Fast OuT of Range (OTR) detection
  • Flexible input voltage range: 1 V p-p to 2 V p-p
  • HVQFN40 package
  • Input bandwidth, 600 MHz
  • Integrated input buffer
  • Offset binary, 2's complement, gray code
  • Pin compatible with the ADC1415S series, ADC1115S series and the ADC1015S
  • series
  • Power-down and Sleep modes
  • Sample rate up to 125 Msps
  • Serial Peripheral Interface (SPI)
  • SNR, 70.5 dBFS
  • SFDR, 90 dBc

製品選択

発注型名 Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete 40 I はい Tray
Availability
Obsolete 40 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
ADC1215S SER Datasheet データシート PDF 377 KB
PCN / PDN
PDN# : DC-14-01 PRODUCT DISCONTINUANCE NOTICE 製品中止通知 PDF 538 KB

ボード&キット

製品名 タイトル 分類 会社名
ADC1215S125F1 ADC1215S125F1 demo board; CMOS version; SPI, Regulators and CMOS buffer on board
ADC1215S125F2 ADC1215S125F2 demo board; SPI, Regulators on board; LVDS output only SAMTEC connector