The 9DBU0641 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated output terminations providing Zo=100 ohms for direct connection to 100 ohm transmission lines. The device has 6 output enables for clock management and 3 selectable SMBus addresses.

特長

  • Direct connection to 100 ohm transmission lines; saves 24 resistors compared to standard PCIe devices
  • 47 mW typical power consumption in PLL mode; minimal power consumption
  • Outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
  • OE# pins; support DIF power management
  • HCSL-compatible differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Outputs blocked until PLL is locked; clean system start-up
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface  works with legacy controllers
  • Space-saving 5x5 mm 40-pin VFQFPN; minimal board space
  • 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
     
 

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active VFQFPN 40 I はい Tray
Availability
Active VFQFPN 40 I はい Reel
Availability
Active VFQFPN 40 C はい Tray
Availability
Active VFQFPN 40 C はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
9DBU0641 Datasheet データシート PDF 3.49 MB
アプリケーションノート、ホワイトペーパー
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs アプリケーションノート PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL アプリケーションノート PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-843 PCI Express Reference Clock Requirements アプリケーションノート PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
その他資料
PCI Express Timing Solutions Overview 概要 PDF 275 KB
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Fanout Buffers Product Overview 製品概要 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 製品概要 PDF 378 KB