The 651S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 651S has best in class Additive Phase Jitter of sub 50 fsec.

Features

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 封装 Buy Sample
651SCMGI Active COL 8 I 是的 Cut Tape Package Info
Availability
651SCMGI8 Active COL 8 I 是的 Reel Package Info
Availability
651SDCGI Active SOIC 8 I 是的 Tube Package Info
Availability
651SDCGI8 Active SOIC 8 I 是的 Reel Package Info
Availability

Documentation & Downloads

文档标题 他の言語 Type 文档格式 文件大小
数据手册与勘误表
651S Datasheet Datasheet PDF 305 KB
应用指南 &白皮书
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
PCN / PDN
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB