The 5P49EE801 is a programmable clock generator intended for low power, battery operated consumer applications. There are four internal PLLs, each individually programmable, allowing for up to eight differrent output frequencies. The frequencies are generated from a single reference clock. The reference clock can come from either a TCXO or fundamental mode crystal. An additional 32kHz crystal oscillator is available to provide a real time clock or non-critical performance MHz processor clock. The 5P49EE801 can be programmed through the use of the I2C interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise. It also may operate in standard spread sepctrum mode. There are total seven 8-bit output dividers. One output bank can be configured to support LVTTL or LVDS. All other outputs are always set to LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

特性

  • Four internal PLLs
  • Internal non-volatile EEPROM
  • Internal I2C EEPROM master interface
  • FAST (400kHz) mode I2C serial interfaces
  • Input Frequencies – TCXO: 10 MHz to 40 MHz – Crystal: 8 MHz to 30 MHz – RTC Crystal: 32.768 kHz
  • Output Frequency Ranges: kHz to 120 MHz
  • Each PLL has an 8-bit reference divider and a 11-bit feedback-divider
  • 8-bit output-divider blocks
  • One of the PLLs support Spread Spectrum generation capable of configuration to pixel rate, with adjustable modulation rate and amplitude to support video clock with no visible artifacts
  • I/O Standards: – Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS – Outputs - 1 pair selectable 3.3 V LVDS
  • 3 independent adjustable VDDO groups.
  • Programmable Slew Rate Control
  • Programmable Loop Bandwidth Settings
  • Programmable output inversion to reduce bimodal jitter
  • Individual output enable/disable
  • Power-down/Sleep mode – 10μA max in power down mode – 32kHz clock output active sleep mode – 100μA max in sleep mode
  • 1.8V VDD Core Voltage
  • Available in 28 pin 4x4mm QFN packages
  • -40 to +85 C Industrial Temp operation

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 28 I 是的 Tube
Availability
Obsolete VFQFPN 28 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
使用指南与说明
VersaClock-LP Low Power Eval Board Setup Guide 手册 - 评估板 PDF 166 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : U-14-01R1 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 527 KB
PDN# : U-14-01 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 531 KB
Downloads
VersaClock 4.3 for Windows Vista Service Pack 2 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows XP Service Pack 2&3 32-bit 软件 ZIP 118.00 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows Vista Service Pack 2 32-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 32-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 32-bit 软件 ZIP 118.54 MB
其他
VersaClock III Eval Board Schematics 原理图 PDF 80 KB
VersaClock3-ProgrammableClocks 产品简述 PDF 1.61 MB
VersaClockLowPower-ProgrammableClocks 产品简述 PDF 1.25 MB
DesignTip-SpreadSpectrumClocking-VersaClock3 产品简述 PDF 199 KB