The 5P83905 is a high-performance, 1-to-6 crystal input to LVCMOS fanout buffer with output enable pins. This device accepts a fundamental mode crystal from 10 MHz to 40 MHz and outputs LVCMOS clocks with best-in-class phase noise performance.

The 5P83905 features a synchronous glitch-free Output Enable function to eliminate any intermediate incorrect output clock cycles when enabling or disabling outputs. It comes in standard TSSOP packages or small QFN packages and can operate from 1.8 V to 3.3 V supplies.

特性

  • Six copies of LVCMOS output clocks with best-in-class phase noise performance
  • Phase Noise:
    Offset Noise Power (3.3 V)
    •      100 Hz: -131 dBc/Hz
    •      1 KHz: -145 dBc/Hz
    •      10 KHz: -154 dBc/Hz
    •      100 KHz: -161 dBc/Hz
  • Operating power supply modes:
    •      Full 3.3 V, 2.5 V, 1.8 V
    •      Mixed 3.3 V core / 2.5 V output operating supply
    •      Mixed 3.3 V core / 1.8 V output operating supply
    •      Mixed 2.5 V core / 1.8 V output operating supply
  • Crystal Oscillator Interface
  • Synchronous Output Enable
  • Packaged in 16-pin TSSOP and QFN packages
  • Extended temperature range (-40°C to +105°C) 

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 封装 Buy Sample
5P83905PGGK Active TSSOP 16 K 是的 Tube Package Info
Availability
5P83905PGGK8 Active TSSOP 16 K 是的 Reel Package Info
Availability
5P83905CMGK Active COL 16 K 是的 Cut Tape Package Info
Availability
5P83905CMGK8 Active COL 16 K 是的 Reel Package Info
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
5P8390x Datasheet Datasheet PDF 459 KB
应用指南 &白皮书
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
PCN / PDN
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
其他
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Ultra-Low-Jitter Single-Ended Buffer Family Overview Overview PDF 252 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB