The MX0141K High-Speed MUX is comprised of a high-speed 1:4 multiplexer (mux) path and a low-speed multi-function control logic path.
The high-speed path is comprised of four passive switches that connects input port “IN” to four output ports “A”, “B”, “C” and “D”. Each of those ports is 16-bit. The passive switches, which closed selectively, forms a bidirectional multiplexer.
The low-speed path is active multi-function IOs that could be configured in different modes. It could configured as unidirectional 1:4 mux with 4-bit port width, 4:16 decoder, or 16-bit signals for port selection. The CIO pins which can be used to drive Chip Enable pins of the NAND Dies, or high-speed mux selector. Both high-speed and low-speed paths support SSTL_12 and SSTL_18 signaling.
- Main Features
- 4 high-bandwidth 16-bit bus multiplexer
- SSTL18 and SSTL12 signaling
- 4 × 11 mm FCCSP package with 0.65/0.5mm ball pitch
- Supports ONFI 3.0, 4.0, 4.1 and Toggle NAND flash
- High-Speed MUX Features
- Bidirectional passive port switches
- Pull-up/pull-down/tristate/bus-hold for deselected ports
- Pin-to-pin output skew < 30ps (within a port)
- Pin-to-pin output skew < 10ps (differential pairs)
- Propagation delay < 150ps
- Insertion loss < 1dB at 800MHz
- Bus holding, weak pull-down or weak pull-up for deselected ports in different configurations via the CFG pins
- Low-Speed MUX/Control Logic Features
- 4-bits in, 16-bits input/output logic targeted for chip enables or port selections
- Multiplexing or decoding
- Unidirectional, active multiplexing
- Multiple function selected via the CFG pins