The 5V2305S is a low skew, single input to five output, clock buffer. The 5V2305S has best in class additive phase jitter of sub 50 fsec.

The 5V2305S also supports a synchronous glitch-free Output Enable function to eliminate any potential intermediate incorrect output clock cycles when enabling or disabling outputs. Available in 16-pin TSSOP and 10-pin DFN packages and can operate from a 1.8 V to 3.3 V supply.

特長

  • Extremely low RMS Additive Phase Jitter: 50 fs
  • Low output skew: 50 ps
  • Packaged in 16-pin TSSOP and small 2mm x 2mm 10-pin DFN
  • Low power CMOS technology
  • Operating voltages of 1.8 V to 3.3 V
  • Extended temperature range (-40°C to +105°C)

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
5V2305SPGGK Preview TSSOP 16 K はい Tube Package Info
Availability
5V2305SPGGK8 Preview TSSOP 16 K はい Reel Package Info
Availability
5V2305SNTGK Preview DFN 10 K はい Cut Tape Package Info
Availability
5V2305SNTGK8 Preview DFN 10 K はい Reel Package Info
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
5V2305S Datasheet Datasheet PDF 210 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
IDT Clock Buffers Offers Ultra Low Additive Phase Jitter Application Note PDF 1.28 MB
Downloads
5V2305 IBIS Model Model - IBIS ZIP 31 KB
5V2305 Hspice Model Model - HSPICE ZIP 33 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English Overview PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English Overview PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English Overview PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English Overview PDF 7.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB