When using the Extended registers (Registers 6 and 7), you can set the bit SPI_R_WN to enable the readback mode of any register. Each register address is provided by its last three bits, called CONTROL BITS. That is the address that needs to be provided to the READBACK_ADDR bits so that the user can read the register with that specific address.

In order to keep the pin compatibility, and some level of software compatibility, the SDO is provided via the MUX_OUT pin, when setting the MUX_OUT bits in Register 2 to 111.

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Documents

タイトル 他の言語 Type 形式 サイズ 日付
データシート
8V97051 Datasheet Datasheet PDF 1.12 MB
その他資料
8V97051 Low-Power Wideband RF Synthesizer / PLL (日本語) English Product Brief PDF 368 KB
8V97051 Low-Power Wideband RF Synthesizer / PLL (日本語) English Product Brief PDF 368 KB