The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT's proprietary phase-locked loop (PLL) analog CMOS technology, the IDT9170B is useful for regenerating clocks in high speed systems where skew is a major concern. By the use of the two select pins, multiples or divisions of the input clock can be generated with zero delay (see Tables 2 and 3). The standard versions produce two outputs, where CLK2 is always a divide by two version of CLK1. The IDT9170B is also useful to recover poor duty cycle clocks. A 50 MHz signal with a 20/80% duty cycle, for example, can be regenerated to the 48/52% typical of the part. The IDT9170B allows the user to control the PLL feedback, making it possible, with an additional 74F240 octal buffer (or other such device that offers controlled skew outputs), to synchronize up to 8 output clocks with zero delay compared to the input. Application notes for the IDT9170B are available. Please consult IDT.

特性

  • On-chip Phase-Locked Loop for clocks synchronization.
  • Synchronizes frequencies up to 107 MHz (output) @ 5.0 V
  • ±1ns skew (max) between input & output clocks @ 5.0 V
  • Can recover poor duty cycle clocks
  • CLK1 to CLK2 skew controlled to within ±1ns @ 5.0 V
  • 3.0 - 5.5 V supply range
  • Low power CMOS technology
  • Small 8-pin DIP or SOIC package
  • On chip loop filter
  • IDT9170B-01 for output clocks 20-107 MHz @ 5.0 V, 20 - 66.7 MHz @ 3.3 V
  • IDT9170B-02 for output clocks 5-26.75 MHz @ 5.0 V, 5 - 16.7 MHz @ 3.3 V

产品选择

下单器件 ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete 8 C 是的 Tube
Availability
Obsolete 8 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9170B Datasheet 数据手册 PDF 376 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : K-13-01R2 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 125 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
PDN# : K-13-01R1 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 125 KB
PDN# : K-13-01 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 122 KB
PCN# : A1208-01R1 Gold to Copper Wire 产品变更通告 PDF 254 KB