The 9FGV1002 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1002 provides four spread-spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

特性

  • PCIe Gen1–5 compliant
  • PCIe Gen5 Common Clock jitter < 83fs RMS
  • 276fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
  • 4 programmable output pairs plus 2 LVCMOS REF outputs
  • 1 integer, fractional or spread-spectrum output frequency per configuration
  • 1MHz–325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz–200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V to 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – see AN-891
  • 4 × 4 mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software

产品选择

This device is factory-configurable. Try the Custom Part Configuration Utility.
下单器件 ID Part Status Pkg. Type Supply Voltage (V) Output Impedance Xtal Freq (MHz) Carrier Type Buy Sample
Active VFQFPN 1.8, 2.5, 3.3 85, 100 8 - 50 Tray
Availability
Active VFQFPN 1.8, 2.5, 3.3 85, 100 8 - 50 Reel
Availability
Active LGA 1.8, 2.5, 3.3 85, 100 8 - 50 Tray
Availability
Active LGA 1.8, 2.5, 3.3 85, 100 8 - 50 Reel
Availability
Active VFQFPN , 1.8, 2.5, 3.3 85, 100 8 - 50 Tray
Availability
Active VFQFPN , 1.8, 2.5, 3.3 85, 100 8 - 50 Reel
Availability
Active VFQFPN , 3.3 100 25 Tray
Availability
Active VFQFPN , 3.3 100 25 Reel
Availability
Active VFQFPN , , , 1.8 100 25 Tray
Availability
Active VFQFPN , 1.8 100 25 Reel
Availability
Active VFQFPN , , , 3.3 85 25 Tray
Availability
Active VFQFPN , 3.3 85 25 Reel
Availability
Active LGA , , , 3.3 100 50 Tray
Availability
Active LGA , 3.3 100 50 Reel
Availability
Active LGA , , , 1.8 100 50 Tray
Availability
Active LGA , 1.8 100 50 Reel
Availability
Active LGA , 3.3 85 50 Tray
Availability
Active LGA , 3.3 85 50 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9FGV1002CQ515 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002C001 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002C002 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002C015 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002CQ505 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002CQ506 Datasheet Addendum 数据手册 PDF 150 KB
9FGV1002C-9FGV1006C Datasheet 数据手册 PDF 414 KB
使用指南与说明
9FGV100x Register Descriptions and Programming Guide 手册 - 软件 PDF 401 KB
应用指南 &白皮书
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : PCN200009 PhiClock Family Revision Update 产品变更通告 PDF 143 KB
Downloads
9FGV1002B PhiClock Timing Commander Personality File v1.5 (TCv1.2) 软件 ZIP 6.17 MB
9FGV1002 IBIS Model 模型 - IBIS ZIP 98 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB