When using the Extended registers (Registers 6 and 7), you can set the bit SPI_R_WN to enable the readback mode of any register. Each register address is provided by its last three bits, called CONTROL BITS. That is the address that needs to be provided to the READBACK_ADDR bits so that the user can read the register with that specific address.

In order to keep the pin compatibility, and some level of software compatibility, the SDO is provided via the MUX_OUT pin, when setting the MUX_OUT bits in Register 2 to 111.

For other questions not addressed by the knowledge base, please submit a technical support request.


文档标题 他の言語 Type 文档格式 文件大小
8V97051 Datasheet Datasheet PDF 1.12 MB
8V97051 Low-Power Wideband RF Synthesizer / PLL 日本語 Product Brief PDF 368 KB