The 82P33831 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

Features

  • SMU allows any IEEE 1588 software, running on an external processor, to control the generation of electical clocks, and to access and control physical layer synchronization
  • Supports Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per G.8273.2 with physical layer frequency support to the DCOs
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • 24 hour time holdover is supported by DCOs with fine frequency resolution (1.7e-16)
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • IEEE 1588 grand master applications are supported by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package

Product Options

Orderable Part ID Part Status Pkg. Code Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82P33831ABAG Active BAG144 C Yes Tray
Availability
82P33831ABAG8 Active BAG144 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
82P33831 Datasheet Datasheet PDF 1.05 MB
Application Notes & White Papers
SyncE Wander Testing for Marvell 88X3340P and IDT 82P33731 White Paper White Paper PDF 523 KB
AN-888 SMU for IEEE 1588 and Synchronous Ethernet 82P338xx/339xx Register Map Application Note PDF 666 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs Application Note PDF 214 KB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 475 KB
ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PCNs & PDNs
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages Product Change Notice PDF 93 KB
PCN# : N1412-01 Die revision change 82P33814, 82P33831, 82P33714, 82P33731, 82P33810 Product Change Notice PDF 40 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Wired Broadband Applications Application Briefs PDF 686 KB
Timing Fabric for Next Generation Communications Equipment Overview 日本語, 简体中文 Overview PDF 1.31 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB

Software & Tools

Title Other Languages Type Format File Size Date
Timing Commander Installer (v1.14.0.24414) Software ZIP 19.57 MB
82P33831 BSDL Model - BSDL BSD 20 KB
82P33x31 Timing Commander Personality Software TCP 4.00 MB
82P33x31_APLL3 Timing Commander Personality Software TCP 1024 KB
82P33831A IBIS Model - IBIS IBS 1.10 MB

Evaluation Boards

Part Number Title Sort ascending
82EBP33831 Evaluation Board for 82P33831 Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet