The 8A34001 System Synchronizer for IEEE 1588 generates ultra-low jitter; precision timing signals based on the IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE).  The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Digitally Controlled Oscillators (DCOs) are available to be controlled by IEEE 1588 clock recovery servo software running on an external processor. The device supports physical layer timing with Digital PLLs (DPLLs) and other timing blocks necessary to implement a Synchronous Equipment Timing Source (SETS) for SyncE. The DCOs can be controlled using IEEE 1588 information alone, or they can combine IEEE 1588 time information with physical layer frequency information from SyncE in accordance with ITU-T G.8273.2. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 Time Stamp Units (TSUs) in a system. The device supports multiple independent channels that control: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Eight independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 0.5Hz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • DCOs can be controlled by external IEEE 1588 software to synthesize Precision Time Protocol (PTP) / IEEE 1588 clocks with frequency resolution less than 1.11x10-16
    • Combo Bus simplifies compliance with ITU-T G.8273.2
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI

Product Options

Orderable Part ID Part Status Pkg. Code Temp. Range Carrier Type Buy Sample
8A34001C-000AJG Active AJG144D1 -40 to 85°C Tray
Availability
8A34001C-000AJG8 Active AJG144D1 -40 to 85°C Reel
Availability
8A34001PC-000AJG Active AJG144D1 -40 to 85°C Tray
Availability
8A34001PC-000AJG8 Active AJG144D1 -40 to 85°C Reel
Availability
8A34001B-000AJG Active AJG144 -40 to 85°C Tray
Availability
8A34001B-000AJG8 Active AJG144 -40 to 85°C Reel
Availability
8A34001PB-000AJG Active AJG144 -40 to 85°C Tray
Availability
8A34001PB-000AJG8 Active AJG144 -40 to 85°C Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
8A3xxxx Family Errata (Rev B with Update v4.7) Errata PDF 127 KB
8A34001 Datasheet Datasheet PDF 1.43 MB
User Guides & Manuals
8A34xxx 144BGA EVK User Manual Manual - Eval Board PDF 2.53 MB
8A3xxxx Family Programming Guide (v4.7) Guide PDF 3.31 MB
Application Notes & White Papers
AN-1034 Minimizing Backplane Signal Usage Application Note PDF 437 KB
AN-1031 Time Alignment Background in Wireless Infrastructure Application Note PDF 392 KB
AN-1033 Delay Variation Measurement and Compensation Application Note PDF 401 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System Application Note PDF 354 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment Application Note PDF 864.15 MB
AN-1020 ClockMatrix on nCXO Redundancy Application Note PDF 530 KB
AN-1010 ClockMatrix Time-to-Digital Converter Application Note PDF 1.54 MB
ClockMatrix GUI Step-by-Step User Guide Application Note PDF 4.98 MB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB
PCNs & PDNs
PCN#: TP1902-02 ROM Update for ClockMatrix Products Product Change Notice PDF 435 KB
Other
ClockMatrix Family Overview Overview PDF 241 KB
8A3x0xx Schematic Checklist (v1.19) Miscellaneous XLSX 303 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
ClockMatrix 144-BGA Devices Evaluation Board Schematic v1.1 Schematic PDF 288 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Software & Tools

Title Other Languages Type Format File Size Date
Timing Commander Installer (v1.13.1.21509) Software ZIP 20.40 MB
Timing Commander Personality File for ClockMatrix 8A34001 (v6.0.2, FWv4.7.0) Software ZIP 12.20 MB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 Software ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 Software ZIP 177 KB
ClockMatrix Register Header Files v4.7 Software ZIP 293 KB
8A340x1 BSDL Model Model - BSDL BSDL 15 KB
8A340xx Clock Matrix IBIS Model Model - IBIS ZIP 2.40 MB
ClockMatrix BGA-144 Delphi Thermal Model with 1W Power Model - Thermal PDML 3 KB
ClockMatrix BGA-144 2-Resistor Thermal Model with 1W Power Model - Thermal PDML 2 KB

Evaluation Boards

Part Number Title Sort ascending
8A34001-EVK Evaluation Kit for 8A34001 ClockMatrix