WAN PLL With Single Reference Input

The 82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3001A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3001A is compliant with AT&T TR62411, Telcordia GR- 1244-CORE Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/ wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The 82V3001A can be used in synchronization and timing control for T1 and E1 systems, or used as ST-BUS clock and frame pulse sources. It can also be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs and line cards.

Features

  • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
  • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
  • Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz
  • Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o
  • Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, F32o, RSP and TSP
  • Holdover frequency accuracy of 0.025 ppm
  • Phase slope of 5 ns/125 ?s
  • Attenuates wander from 2.1 Hz
  • Fast Lock mode
  • Provides Time Interval Error (TIE) correction
  • MTIE of 600 ns
  • JTAG boundary scan
  • Holdover status indication
  • Freerun status indication
  • Normal status indication
  • Lock status indication
  • 3.3 V operation with 5 V tolerant I/O
  • Package available: 56-pin SSOP (Green option available)

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82V3001APVG Active PVG56 SSOP 56 C Yes Tube Availability
82V3001APVG8 Active PVG56 SSOP 56 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
82V3001A Data Sheet Datasheet PDF 143 KB Sep 30, 2014
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB Oct 27, 2016
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1506-02 Gold wire to Copper wire Product Change Notice PDF 35 KB Oct 7, 2015
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 14, 2014
PDN# : CQ-13-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 302 KB Jul 24, 2013
Other
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

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