The 9DBL0951 device is a member of IDT's 3.3V full-featured PCIe clock family. The 9DBL0951 device supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. The device's integrated output terminations provide a direct connection to 85Ω transmission lines. The 9DBL09P1 can be factory programmed with a user-defined power up default SMBus configuration.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

Features

  • PCIe Gen1–4 CC compliant
  • Supports PCIe Gen2–3 SRIS compliant
  • Supports PCIe SRnS compatible
  • Direct connection to 85Ω transmission lines; saves 36 resistors compared to standard PCIe devices
  • Spread spectrum tolerant; allows reduction of EMI
  • Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Easy AC-coupling to other logic families; see IDT application note AN-891.
  • Space saving 6 x 6 mm 48-VFQFPN; minimal board space

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
9DBL0951BKILF Active NDG48P2 VFQFPN 48 I 85 Tray
Availability

Buy / Quote
9DBL0951BKILFT Active NDG48P2 VFQFPN 48 I 85 Reel
Availability
Buy / Quote

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBL09 Datasheet – Datasheet PDF 287 KB
User Guides & Manuals
Timing Products for NXP (Freescale) i.MX 简体中文 Guide PDF 321 KB
Application Notes & White Papers
AN-975 Cascading PLLs – Application Note PDF 128 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs – Application Note PDF 354 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 150 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.81 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 349 KB
AN-839 RMS Phase Jitter – Application Note PDF 149 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units – Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 38 KB
Other
9DBL09xx Reference Schematic – Schematic PDF 18 KB
Timing Solutions Products Overview – Overview PDF 4.11 MB
PCI Express® Timing Solutions Overview – Overview PDF 301 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Software & Tools

Title Other Languages Type Format File Size Date
9DBL0951 IBIS Model – Model - IBIS ZIP 63 KB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Dec 18, 2017
Why Fanout Buffers Make More Sense Nov 28, 2017
Time for Performance Oct 11, 2017
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped Dec 18, 2014