6-output 1.5 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DBU0631 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 6 output enables for clock management and 3 selectable SMBus addresses.

Features

  • Direct connection to 100 ohm transmission lines; saves 12 resistors compared to standard PCIe devices
  • 47 mW typical power consumption in PLL mode; minimal power consumption
  • Outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
  • OE# pins; support DIF power management
  • HCSL-compatible differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Outputs blocked until PLL is locked; clean system start-up
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface  works with legacy controllers
  • Space saving 5x5 mm 40-pin VFQFPN; minimal board space
  • 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
 

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9DBU0631AKILF Active NDG40P2 VFQFPN 40 I Yes Tray Availability
9DBU0631AKILFT Active NDG40P2 VFQFPN 40 I Yes Reel Availability
9DBU0631AKLF Active NDG40P2 VFQFPN 40 C Yes Tray Availability
9DBU0631AKLFT Active NDG40P2 VFQFPN 40 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBU0631 Datasheet Datasheet PDF 222 KB Oct 28, 2015
Application Notes & White Papers
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 7, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
IDT PCI Express Solutions Overview 日本語, 简体中文 Overview PDF 768 KB Apr 19, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 13, 2012

Software & Tools

Title Other Languages Type Format File Size Date
9DBU0631 IBIS Model Model - IBIS ZIP 21 KB Jan 22, 2015