The 9DBU0741 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 ohm transmission lines. The device has 7 output enables for clock management, and 3 selectable SMBus addresses.

Features

  • Integrated terminations; save 28 resistors compared to standard HCSL outputs
  • 36 mW typical power consumption; minimal power consumption
  • OE# pin for each output; support DIF power management
  • HCSL differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • 1 MHz to 167 MHz operating frequency
  • 3.3 V tolerant SMBus interface; works with legacy controllers
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment
  • Device contains default configuration; SMBus interface not required for device operation
  • Space-saving 5x5 mm 40-pin VFQFPN; minimal board space

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9DBU0741AKILF Active NDG40P2 VFQFPN 40 I Yes Tray
Availability

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9DBU0741AKILFT Active NDG40P2 VFQFPN 40 I Yes Reel
Availability
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9DBU0741AKLF Active NDG40P2 VFQFPN 40 C Yes Tray
Availability

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9DBU0741AKLFT Active NDG40P2 VFQFPN 40 C Yes Reel
Availability
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Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBU0741 Datasheet – Datasheet PDF 213 KB Mar 8, 2017
Application Notes & White Papers
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs – Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 150 KB Apr 7, 2015
AN-844 Termination - AC Coupling Clock Receivers – Application Note PDF 82 KB May 12, 2014
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.81 MB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 349 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units – Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads – Application Note PDF 38 KB Jan 14, 2014
Other
Timing Solutions Products Overview – Overview PDF 4.11 MB Oct 31, 2018
PCI Express® Timing Solutions Overview – Overview PDF 301 KB Apr 19, 2018
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
IDT Fanout Buffers Product Overview – Product Brief PDF 739 KB Feb 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief – Product Brief PDF 378 KB Aug 13, 2012
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Dec 18, 2017
Why Fanout Buffers Make More Sense Nov 28, 2017
Time for Performance Oct 11, 2017
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped Dec 18, 2014
IDT Announces 1.5 Volt PCI Express® Clock Buffer Family Offering Industry-leading Space and Power Savings Jul 23, 2014