4-output 1.8 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer with Zo=100 ohms

The 9DBV0441 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo=100ohms for direct connection to 100ohm transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.

Features

  • Direct connection to 100ohm transmission lines; saves 16 resistors compared to standard HCSL outputs
  • 53mW typical power consumption in PLL mode; minimal power consumption
  • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
  • OE# pins: support DIF power management
  • HCSL compatible differential input: can be driven by common clock sources
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
  • Outputs blocked until PLL is locked: clean system start-up
  • Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet Applications
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space-saving 5x5 mm 32-pin VFQFPN: minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9DBV0441AKILF Active NLG32P3 VFQFPN 32 I Yes Tray Availability
9DBV0441AKILFT Active NLG32P3 VFQFPN 32 I Yes Reel Availability
9DBV0441AKLF Active NLG32P3 VFQFPN 32 C Yes Tray Availability
9DBV0441AKLFT Active NLG32P3 VFQFPN 32 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBV0441 Datasheet Datasheet PDF 206 KB Apr 28, 2016
Application Notes & White Papers
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 7, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB Dec 19, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
Other
IDT PCI Express Solutions Overview 日本語, 简体中文 Overview PDF 768 KB Apr 19, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
Automotive Solutions Overview 简体中文 Overview PDF 2.79 MB Mar 8, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 16, 2015
9DBV0441 Reference Schematic Schematic PDF 72 KB Jan 22, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 13, 2012

Software & Tools

Title Other Languages Type Format File Size Date
9DBV0441 IBIS Model Model - IBIS ZIP 70 KB Dec 2, 2015