The PCIe data channel is a high speed serial communication interface with speeds up to 8 Gb/s, increasing to 16 Gb/s when PCIe Gen4 devices become available. As with any serial communication interface, the most critical clock parameter is phase jitter. This makes PCIe clock generators the heart of PCIe timing and the gating factor in system performance and reliability. A PCIe-based system with a lower-performance clock may completely fail to train. More insidiously, the link may train to less than the advertised throughput, or will experience many link errors thus requiring data be resent. These last two items are insidious because while the system will function, performance will be degraded due to the reduced link bandwidth.
IDT PCIe clock generators provide 1 to 8 outputs, exceeding the published PCIe specifications at each performance node, PCIe Gen1, Gen2 and Gen3 (and soon to be Gen4). IDT also offers these high performance clock generators in 1.5V, 1.8V or 3.3V versions, allowing the designer to power their PCIe clock generators from the same power supply as their FPGA or System on a Chip (SoC). The IDT PCIe Generators are offered with integrated terminations to allow direct connection of the outputs to the transmission line, thus saving significant board space.
Download: PCIe Measurement Techniques for Gen5 and Beyond White Paper (PDF)
Download: IDT PCI Express Solutions Overview (PDF | English, 日本語, 简体中文)