2:12 DB1200ZL Derivative Low Power HCSL Clock Mux

The 9ZML1233E is a second generation enhanced performance DB1200ZL derivative. The part is a pin-compatible
upgrade to the 9ZML1232B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1233E has an SMBus Write Lockout pin for increased device and system security.

Features

  • SMBus write lock feature; increases system security
  • 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
  • LP-HCSL outputs; eliminate 24 resistors, save 41mm² of area
  • 12 OE# pins; hardware control of each output
  • 3 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL bandwidths; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL Mode; UPI support
  • 10 x 10 mm 72-VFQFPN package; small board footprint

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZML1233EKILF Active NLG72P1 VFQFPN 72 I Yes Tray Availability
9ZML1233EKILFT Active NLG72P1 VFQFPN 72 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZML1233E_1253E Datasheet Datasheet PDF 314 KB Apr 12, 2018
Application Notes & White Papers
AN-1001 Combining PhiClock™ and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 103 KB Mar 12, 2018
AN-975 Cascading PLLs Application Note PDF 128 KB Aug 2, 2017
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 7, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB Jan 14, 2014
Other
PCI Express® Timing Solutions Overview Overview PDF 301 KB Apr 19, 2018
The IDT Communications Products Advantage Overview PDF 4.00 MB Mar 21, 2018
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Evaluation Boards

Part Number Title Sort ascending
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI