12-Output DB1200ZL Derivative with Integrated 85Ω Terminations

The 9ZXL1252E is a second-generation, enhanced-performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZLX1252A, while offering a much improved phase jitter performance and an SMBus Write Lock feature for increased system security. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL1252E has an SMBus Write Lockout pin for increased device and system security.

Features

  • SMBus write lock feature; increases system security
  • LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
  • 12 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
  • 9 x 9 mm 64-QFN package; small board footprint

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL1252EKILF Active NLG64P2 VFQFPN 64 I Yes Tray Availability
9ZXL1252EKILFT Active NLG64P2 VFQFPN 64 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZXL1232E_1252E Datasheet Datasheet PDF 340 KB Apr 17, 2018
Application Notes & White Papers
AN-1001 Combining PhiClock™ and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 103 KB Mar 12, 2018
AN-975 Cascading PLLs Application Note PDF 128 KB Aug 2, 2017
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 7, 2015
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB Jan 14, 2014
Other
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
9ZXL1252E IBIS Model Model - IBIS ZIP 25 KB Jan 11, 2018

Evaluation Boards

Part Number Title Sort ascending
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI