The IDT 8P34S1212I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1212I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1212I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Twelve low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK0, PCLK1 pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 1.2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control input select pin
  • Output skew: 12ps (typical)
  • Propagation delay: 365ps (VPP = 0.1V, typical)
  • Low additive phase jitter, RMS
  • fREF = 156.25MHz, VPP = 1V, 12kHz- 20MHz: 73.11 fs (typical)
  • Maximum device current consumption (IDD): 205mA (maximum) @ 1.89V
  • Full 1.8V supply voltage
  • Lead-free (RoHS 6), 40-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8P34S1212NLGI Active NLG40P2 VFQFPN 40 I Yes Tray
Availability
8P34S1212NLGI8 Active NLG40P2 VFQFPN 40 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
IDT8P34S1212I Datasheet Datasheet PDF 545 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCNs & PDNs
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : TB1311-01 New Carrier Tape on VFQFPN-28, VFQFPN-40, VFQFPN-48 Product Change Notice PDF 790 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
RF Timing Family Product Overview Overview PDF 723 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Software & Tools

Title Other Languages Type Format File Size Date
8P34S1212I IBIS Model Model - IBIS ZIP 37 KB