Dual 1:4 LVDS Output 1.8V Fanout Buffer

The 8P34S2104 is a high-performance, low-power, differential dual 1:4 LVDS Output 1.8V Fanout Buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has four low skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2104 ideal for those clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs.

Features

  • Dual 1:4 low skew, low additive jitter LVDS fanout buffers
  • Matched AC characteristics across both channels
  • High isolation between channels
  • Low power consumption
  • Both differential CLKA, nCLKA and CLKB, nCLKB inputs accept LVDS, LVPECL and single-ended LVCMOS levels
  • Maximum input clock frequency: 2.0GHz
  • Output amplitudes: 350mV, 500mV (selectable)
  • Output bank skew: 5ps typical
  • Output skew: 30ps typical
  • Low additive phase jitter, RMS: 40fs typical (fREF = 156.25MHz, 12kHz to 20MHz)
  • Full 1.8V supply voltage mode
  • Lead-free (RoHS 6), 28-lead VFQFN packaging
  • -40°C to 85°C (Tc ≤ 105°C) operating temperature range

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Tape Pin 1 Quad Pb (Lead) Free Carrier Type Buy Sample
8P34S2104NBGI Active NBG28 VFQFPN 28 I 1 Yes Tray Availability
8P34S2104NBGI8 Active NBG28 VFQFPN 28 I 1 Yes Reel Availability
8P34S2104NBGI/W Active NBG28 VFQFPN 28 I 1 Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
8P34S2104 Datasheet Datasheet PDF 433 KB Oct 24, 2016
Application Notes & White Papers
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
8P34S21xx-series 1.8V Dual RF Clock / Data Fanout Buffers Product Brief PDF 291 KB Nov 20, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016