The 8SLVD2104 is a high-performance differential dual 1:4 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2104 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2104 ideal for those clock distribution applications demanding well-defined performance and
repeatability. Two independent buffers with four low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Two 1:4, low skew, low additive jitter LVDS fanout buffers
  • Two differential clock inputs
  • Differential pairs can accept the following differential input levels: LVDS and LVPECL
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 35ps, (maximum)
  • Propagation delay: 300ps, (maximum)
  • Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz):  105fs, (maximum)
  • 2.5V supply voltage
  • Lead-free (RoHS 6) 28-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8SLVD2104NBGI Active NBG28 VFQFPN 28 I Yes Tray
Availability
8SLVD2104NBGI/W Active NBG28 VFQFPN 28 I Yes Reel
Availability
8SLVD2104NBGI8 Active NBG28 VFQFPN 28 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
8SLVD2104 Final Data Sheet Datasheet PDF 430 KB
Application Notes & White Papers
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
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