Low Phase Noise,1-to-4, 3.3V, 2.5V LVPECL Output Fanout Buffer

The IDT8SLVP1104I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVP1104I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVP1104I ideal for those clock distribution applications demanding well-defined performance and
repeatability.Four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Four low skew, low additive jitter LVPECL differential output pairs
  • Differential LVPECL input pair can accept the following differential input levels: LVDS, LVPECL, CML
  • Differential PCLKx pairs can also accept single-ended LVCMOS levels. See the Applications section Writing the Differential Input Levels to Accept Single-ended Levels (Figures 1 and 2)
  • Maximum input clock frequency: 2GHz 
  • LVCMOS interface levels for the control input (input select) 
  • Output skew: 5ps (typical)
  • Propagation delay: 320ps (maximum)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 40fs (maximum)
  • Maximum device current consumption (IEE): 60mA (maximum)
  • Full 3.3V or 2.5V supply voltage
  • Lead-free (RoHS 6) packaging
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8SLVP1104ANLGI Active NLG16P2 VFQFPN 16 I Yes Tube Availability
8SLVP1104ANLGI8 Active NLG16P2 VFQFPN 16 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
IDT8SLVP1104I Datasheet Datasheet PDF 370 KB Feb 28, 2014
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

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