1:18, 2.5V, 3.3V Selectable LVPECL or LVDS Fanout Buffer

The 8SLVS1118 is a high-performance, low-power, differential 1:18 output fanout buffer. This highly versatile device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVS1118 ideal for clock distribution applications that demand well-defined performance and repeatability. The device is characterized to operate from a 2.5V or 3.3V power supply. The integrated bias voltage references enable easy interfacing AC-coupled signals to the device inputs.

Features

  • 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer 
  • Low power consumption 
  • Differential PCLK, nPCLK clock pair accepts the following differential/single-ended input levels: LVDS, LVPECL, and LVCMOS 
  • Maximum input clock frequency: 2GHz 
  • Propagation delay: 290ps (typical) 
  • Output skew: 40ps (typical) 
  • Low additive phase jitter, RMS: 39fs (typical)
  • Integration range: 12kHz–20MHz (fREF = 156.25MHz, VPP = 1V, VDD = 3.3V) 
  • Full 2.5V and 3.3V supply voltage modes 
  • Device current consumption:
    • 180mA (typical) IEE for LVPECL output mode
    • 400mA (typical) IDD for LVDS output mode 
  • 48-VFQFN, lead-free (RoHS 6) packaging 
  • Transistor count: 1762
  • -40°C to +85°C ambient operating temperature 
  • Supports case temperature up to 105°C

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8SLVS1118NLGI Active NLG48P1 VFQFPN 48 I Yes Tray Availability
8SLVS1118NLGI/W Active NLG48P1 VFQFPN 48 I Yes Reel Availability
8SLVS1118NLGI8 Active NLG48P1 VFQFPN 48 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
8SLVS1118 Datasheet Datasheet PDF 683 KB Jul 17, 2017
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016