Low Skew 1 to 4 Clock Buffer

The 621S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 621S has best in class Additive Phase Jitter of sub 50 fsec.

Features

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
621SCMGI Active CMG8 COL 8 I Yes Cut Tape
Availability
621SCMGI8 Active CMG8 COL 8 I Yes Reel
Availability
621SDCGI Active DCG8 SOIC 8 I Yes Tube
Availability
621SDCGI8 Active DCG8 SOIC 8 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
621S Datasheet Datasheet PDF 215 KB Mar 18, 2015
Application Notes & White Papers
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
PCNs & PDNs
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 13, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 14, 2016
Other
Timing Solutions Products Overview Overview PDF 4.11 MB Oct 31, 2018
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
621S IBIS Model Model - IBIS ZIP 22 KB Nov 16, 2018