2:4 HCSL PCIe Clock Buffer

The 831724I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the multiplexing and fanout of high-frequency clock and data signals. The device has two differential, selectable clock/data inputs. The selected input signal is distributed to four low-skew differential HCSL outputs. Each input pair accepts HCSL, LVDS, LVPECL and SSTL levels. The 831724I is characterized to operate from a 3.3V power supply. Guaranteed input, output-to-output and part-to-part skew characteristics make the 831724I ideal for those clock and data distribution applications demanding well-defined performance and repeatability. The 831724I supports the clock multiplexing and distribution of PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/s) clock signals. The device is a member of the family of High Performance Clock Solutions from IDT.

Features

  • 2:1 differential clock/data multiplexer with fanout
  • Two selectable, differential inputs
  • Each differential input pair can accept the following levels: HCSL, LVDS, LVPECL
  • Four differential HCSL outputs
  • Maximum input/output clock frequency: 350MHz
  • Maximum input/output data rate: 700Mb/s (NRZ)
  • LVCMOS interface levels for all control inputs
  • PCI Express Gen 1,2,3 jitter compliant
  • Input skew: 165ps (maximum)
  • Output skew: 175ps (maximum)
  • Part-to-part skew: 450ps (maximum)
  • Full 3.3V supply voltage
  • Available in lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
831724AKILF Active NLG32P1 VFQFPN 32 I Yes Tray Availability
831724AKILFT Active NLG32P1 VFQFPN 32 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
831724 Datasheet Datasheet PDF 490 KB Nov 16, 2016
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB Dec 19, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
831724I IBIS Model - IBIS ZIP 1.35 MB May 27, 2013

News & Additional Resources