Low Skew,1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

The 83940D is a low skew, 1-to-18 LVPECL-to- LVCMOS/LVTTL Fanout Buffer. The 83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940D is characterized at full 3.3V and 2.5V or mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • 18 LVCMOS/LVTTL outputs
  • Selectable LVCMOS_CLK or LVPECL clock inputs
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 250MHz
  • Output skew: 150ps (maximum)
  • Part to part skew: 750ps (maximum)
  • Additive phase jitter, RMS: < 0.03ps (typical)
  • Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes
  • 0°C to 70°C ambient operating temperature
  • Lead-Free package available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
83940DYLF Active PRG32 TQFP 32 C Yes Tray Availability
83940DYLFT Active PRG32 TQFP 32 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
83940D Datasheet Datasheet PDF 214 KB Mar 24, 2015
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 13, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 14, 2016
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 21, 2015
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 20, 2015
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 10, 2013
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
83940D IBIS Model Model - IBIS ZIP 78 KB Nov 25, 2009

News & Additional Resources