Differential-to-LVDS Fanout Buffer W/Divider And Glitchless Switch

NOTICE - The following device(s) are recommended alternatives:

The 854S1208I is a low skew, 8 output LVDS Fanout Buffer with selectable divider. The 854S1208I has 2 selectable inputs that accept a variety of differential input types. The device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The output enable pins assigned to each output, support enabling and disabling each output individually. The 854S1208I is characterized at full 3.3V or 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 854S1208I ideal for high performance applications.

Features

  • Eight differential LVDS output pairs Each output has individual synchronous output enable
  • Two selectable differential CLKx, nCLKx input pairs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HCSL
  • Maximum output frequency: 1.5GHz
  • Independent bank control for ÷1 or ÷2 operation
  • Glitchless output behavior during input switch
  • Output skew: 40ps (maximum)
  • Bank skew: 35ps (maximum)
  • Full 3.3V or 2.5V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
854S1208AYILF Last Time Buy DXG48P2 PTQFP 48 I Yes Tray Availability
854S1208AYILFT Last Time Buy DXG48P2 PTQFP 48 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
854S1208I Datasheet PDF 1.36 MB May 1, 2012
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-17-04(R1) Product Discontinuance Notice Product Discontinuation Notice PDF 606 KB Nov 29, 2017
PCN# : A1709-02 Add alternate assembly at OSET and Convert to Copper Wire Product Change Notice PDF 35 KB Sep 26, 2017
PDN# : CQ-17-04 Product Discontinuance Notice Product Discontinuation Notice PDF 599 KB Aug 24, 2017
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 10, 2013
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

News & Additional Resources