Dual 1:4 Fanout Buffer with 1.0V Single-Ended Inputs and Outputs

The 9SBV0802 provides two banks of four 1.05V LVCMOS outputs. Each bank has its own input. There are three OE pins. Two OE pins control two outputs each and one OE pin controls four outputs. One 9SBV0802 allows one PCH to easily support four CPU's with point to point routing of the PM signals. Two 9SBV0802 devices allow one PCH to easily support up to eight CPU's with point-to-point routing of the PM signals.
 

Features

  • Eight 1–48MHz 1.05V LVCMOS outputs
  • Additive cycle-to-cycle jitter < 8ps
  • Output-to-output skew within a bank < 50ps
  • Output-to-output skew between banks < 100ps
  • 1.8V power supply, 15mW typical power consumption
  • Three OE pins
  • 1.05V LVCMOS inputs with VREF pin
  • Space saving 4 x 4 mm 20-VFQFPN

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Temp. Range Carrier Type Buy Sample
9SBV0802AKILF Active NLG20P1 VFQFPN 20 I -40 to 85°C Tube
Availability
9SBV0802AKILFT Active NLG20P1 VFQFPN 20 I -40 to 85°C Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9SBV0802 Datasheet Datasheet PDF 205 KB Dec 15, 2016
Application Notes & White Papers
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
Other
Timing Solutions Products Overview Overview PDF 4.11 MB Oct 31, 2018
IDT Ultra-Low-Jitter Single-Ended Buffer Family Overview Overview PDF 252 KB Aug 16, 2016
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016