2.5V Single Data Rate 1:5 Clock Buffer Terabuffer™

NOTICE - The following device(s) are recommended alternatives:

The 5T90533I 2.5V single data rate (SDR) clock buffer is a userselectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The 5T90533I can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.

Features

  • Guaranteed Low Skew < 25ps (max)
  • Very low duty cycle distortion
  • High speed propagation delay < 2.5ns. (max)
  • Up to 250MHz operation
  • Very low CMOS power levels
  • 1.5V VDDQ for HSTL interface
  • Hot insertable and over-voltage tolerant inputs
  • 3-level inputs for selectable interface
  • Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
  • Selectable differential or single-ended inputs and five singleended outputs
  • 2.5V VDD
  • Available in TSSOP package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5T90533PGGI Obsolete PGG28 TSSOP 28 I Yes Tube Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
5T90533 Datasheet Datasheet PDF 217 KB Jan 19, 2017
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-15-05 Market Declined Quarterly PDN Product Discontinuation Notice PDF 623 KB Oct 28, 2015
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

News & Additional Resources