1:2 Fanout Buffer With Pre-Emphasis

The 854S712I is a differential, high-speed 1:2 data/clock fanout buffer and line driver. The outputs support pre-emphasis in order to drive backplanes and long transmission lines while reducing inter-symbol interference effects. The pre-emphasis level is configurable to optimize for low bit error rate or power consumption. Pre-emphasis utilizes an increased output voltage swing for transition bits. The device is optimized for data rates up to 4.5 Gbps (NRZ) and for deterministic jitter in data applications and low additive jitter in clock applications. The outputs are LVDS-compliant while the differential input is compatible with a variety of signal levels such as LVDS, LVPECL and CML. Internal input termination, a bias voltage output for AC-coupling and small packaging (VFQFN) supports space-efficient board designs. The 854S712I operates from a 3.3V power supply and supports the industrial temperature range of -40°C to +85°C.

Features

  • 1:2 differential data/clock fanout buffer and line driver
  • 4.5 Gbps data rate (NRZ) (maximum)
  • Differential LVDS outputs
  • Differential input supporting LVDS, LVPECL and CML levels
  • Configurable output pre-emphasis
  • Low-skew outputs: 10ps (maximum)
  • Low data deterministic jitter: 4ps (maximum)
  • LVCMOS interface levels for the control inputs
  • Asynchronous output disable into high-impedance state
  • Internal input termination: 100? (Differential)
  • Additive phase jitter, RMS: 0.08ps (typical)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
854S712AKILF Active NLG16 VFQFPN 16 I Yes Tube Availability
854S712AKILFT Active NLG16 VFQFPN 16 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
854S712 Datasheet Datasheet PDF 447 KB Oct 10, 2017
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 10, 2013
Other
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB Nov 29, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 13, 2012

Software & Tools

Title Other Languages Type Format File Size Date
854S712I IBIS Model Model - IBIS ZIP 65 KB Aug 24, 2010

News & Additional Resources