The 571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the 570. The 571, part of IDT's ClockBlocks™ family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the 571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two.

Features

  • Packaged in 8-pin SOIC (Pb free)
  • Can function as low phase noise x2 multiplier
  • Low skew outputs. One is ÷2 of other
  • Input clock frequency up to 160 MHz at 3.3 V
  • Phase noise of better than -100 dBc/Hz from 1 kHz to 1 MHz offset from carrier
  • Can recover poor input clock duty cycle
  • Output clock duty cycle of 45/55 at 3.3 V
  • High drive strength for >100 MHz outputs
  • Full CMOS clock swings with 25 mA drive capability at TTL levels
  • Advanced, low power CMOS process
  • Operating voltages of 3.0 to 5.5 V

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
571MLF Obsolete DCG8 SOIC 8 C Yes Tube
Availability
571MLFT Obsolete DCG8 SOIC 8 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
571 Datasheet Datasheet PDF 183 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 245 KB
PCNs & PDNs
PDN# : CQ-18-03 Product Discontinuance Notice Product Discontinuation Notice PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Software & Tools

Title Other Languages Type Format File Size Date
571 3.3V IBIS Model Model - IBIS ZIP 3 KB