Low Phase Noise Zero Delay Buffer and Multiplier

The ICS670-02 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT’s ClockBlocksTM family, the part’s zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin. The ICS670-02 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data
communications to video. By allowing off-chip feedback paths, the chip can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including functional multipliers, see the ICS527.

Features

  • Packaged in 16-pin SOIC
  • Pb (lead) free package, RoHS compliant
  • Clock inputs from 5 to 160 MHz (see page 2)
  • Patented PLL with low phase noise
  • Output clocks up to 160 MHz at 3.3 V
  • 15 selectable on-chip multipliers
  • Power down mode available
  • Low phase noise: -111 dBc/Hz at 10 kHz
  • Output enable function tri-states outputs
  • Low jitter 15 ps one sigma
  • Advanced, low power, sub-micron CMOS process
  • Operating voltage of 3.3 V or 5 V
  • Industrial temperature range available (-40 to +85°C)

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
670M-02LF Active DCG16 SOIC 16 C Yes Tube Availability
670M-02LFT Active DCG16 SOIC 16 C Yes Reel Availability
670MI-02LF Active DCG16 SOIC 16 I Yes Tube Availability
670MI-02LFT Active DCG16 SOIC 16 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ics67002 Datasheet PDF 199 KB May 16, 2010
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 245 KB Sep 11, 2013
PCNs & PDNs
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 13, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 14, 2016
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB Oct 10, 2013
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 20, 2012
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB Oct 5, 2006
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
670-02 3.3V IBIS Model Model - IBIS ZIP 3 KB Mar 9, 2006
670-01 5.0V IBIS Model Model - IBIS ZIP 3 KB Mar 9, 2006
670-01 3.3V IBIS Model Model - IBIS ZIP 3 KB Mar 9, 2006

News & Additional Resources