LVCMOS Clock Generator

The 870919I is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Several output configurations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The LOCK output asserts to indicate when phase-lock has been achieved. The 870919I device is a member of the HiperClocks family of high performance clock solutions from IDT.

Features

  • Two selectable single-ended input reference clocks
  • Eight single-ended clock outputs
  • Internal PLL does not require external loop filter components
  • 5V tolerant inputs
  • Maximum output frequency: 160MHz, (2XQ output)
  • Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)
  • LVCMOS interface levels for all inputs and outputs
  • PLL disable feature for low-frequency testing
  • PLL lock output
  • Selectable synchronization of output to input edge
  • Output drive capability: ±24mA
  • Output skew: 300ps (maximum), Q0:Q4
  • Output skew: 500ps (maximum), all outputs
  • Full 3.3V supply voltage
  • Available in lead-free (RoHS 6) packages
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
870919BRILF Obsolete PCG28 QSOP 28 I Yes Tube Availability
870919BRILFT Obsolete PCG28 QSOP 28 I Yes Reel Availability
870919BVILF Obsolete PLG28 PLCC 28 I Yes Tube Availability
870919BVILFT Obsolete PLG28 PLCC 28 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
870919I Final Data Sheet Datasheet PDF 221 KB Apr 10, 2014
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB Nov 2, 2016
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 23, 2013
Other
The IDT Consumer Products Advantage Overview PDF 4.01 MB Jun 30, 2017
The IDT Automotive Advantage Overview PDF 3.55 MB May 26, 2017
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

News & Additional Resources