Dual Channel DDRII/III Zero Delay Buffer

Features

  • High performance, low jitter zero delay buffer
  • I2C for functional and output control
  • Dual bank 1-6 differential clock distribution
  • 2 separate feedback in & out for input to output
  • synchronization for each bankSupports up to 4 DDR DIMMs
  • Supports up to DDRII - 1066MHz
  • Supports up to DDRIII (1.8V core) - 1333MHz

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9P960AFLF Active PVG48 SSOP 48 C Yes Tube
Availability
9P960AFLFT Active PVG48 SSOP 48 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
9P960 Datasheet Datasheet PDF 131 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCNs & PDNs
PCN# : A1506-02 Gold wire to Copper wire Product Change Notice PDF 35 KB
PCN# : A1504-04 Assembly Transfer from Amkor Philippines to OSE Taiwan Product Change Notice PDF 484 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
PC Clocks Contact Info Misc PDF 62 KB