IDT low jitter clock generators are all PLL-based products that generate one or more clock signals within an application. This category contains low-phase noise oscillators suitable for most serial data applications. These low-jitter clocks are available with various kinds of single-ended or differential signalling levels, such as LVCMOS, LVPECL, LVDS, HCSL, SSTL, HSTL, etc.
Once the clock generator is selected, low additive phase noise fanout buffers can be used to provide additional copies and output types. IDT has the largest selection of low-jitter clocks and low-phase noise oscillators in the industry, which allows for highly optimized solutions. For application-specific lower-jitter clocks (such as PCIe, RF, and network synchronization), click here.
(Hint: If more than one unique output frequency is required (eg. 100MHz and 125Mhz), make use of the “Output Banks” parametric selector. Each bank corresponds to a unique output frequency. The number of outputs per bank is highly variable depending on the device.)
Key Parameters of a Low-Jitter Clock / Low-Phase Noise Oscillator
There are many important factors when choosing a low-jitter clock for a particular application. The following parameters will give users a basic starting point to narrow down the potential solutions:
- phase jitter: defined as the undesired deviation from an ideal periodic timing signal. IDT’s low-jitter clocks offer typical RMS phase jitter of less than 700 fs, with some lower than 300 fs for very high-performance applications.
- output frequency range: the valid range of output frequencies. IDT offers low-phase noise oscillators to address the frequency needs of all popular applications.
- output type: this is the signalling type of the output that is required of the low-jitter clock. IDT offers CML, HCSL, HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, and LVTTL.
- core voltage: the supply voltage used to power the low-phase noise oscillator. This is typically defined by the power rails available in the system, and often has implications on voltage levels of the output. IDT’s low-phase noise clocks are offered in both 2.5 V and 3.3 V options.
About Low-Jitter Clocks (Low-Phase Noise Oscillators)
A low-jitter clock is a sophisticated IC that produces a timing signal for use in synchronizing a system’s operation. At its most basic level, a low-jitter clock consists of a resonant circuit and an amplifier. The resulting timing signal can range from a simple 50 percent duty cycle square wave to more sophisticated arrangements. In this case, the resonant circuit is typically a quartz piezo-electric low -phase noise oscillator. IDT offers several families of low-jitter clocks, with varying levels of power, performance, and flexibility to address virtually any application requiring a low-phase noise oscillator.