The IDT8T49N006I is a six output Clock Generator with selectable LVDS or LVPECL outputs. The IDT8T49N006I can generate any one of four frequencies from a single crystal or reference clock. The four frequencies are selected from the Frequency Selection Table (Table 1) and are programmed via I2C interface. The four predefined frequencies are selected in the user application by two frequency selection pins. Note the desired programmed frequencies must be used with the corresponding crystal or clock frequency as indicated in Table 1. Excellent phase noise performance is maintained with IDT’s Fourth Generation FemtoClock® NG PLL technology, which delivers sub-400fs RMS phase jitter.

Features

  • Fourth Generation FemtoClock NG PLL technology
  • Six selectable LVPECL or LVDS outputs via I2C
  • CLK, nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL
  • FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
  • RMS phase jitter at 156.25MHz (12kHz - 20MHz): 228fs (typical)
  • Full 2.5V or 3.3V power supply
  • I2C programming interface
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • 4-output (8T49N004I) and 8-output (8T49N008I) also available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T49N006A-000NLGI Active NLG40P2 VFQFPN 40 I Yes Tray
Availability
8T49N006A-999NLGI Active NLG40P2 VFQFPN 40 I Yes Tray
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
8T49N006I Datasheet Datasheet PDF 568 KB
User Guides & Manuals
Programmable FemtoClock Ordering Product Information Manual PDF 140 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-831 The Crystal Load curve Application Note PDF 308 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 50 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PCNs & PDNs
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : W1308-01 Change of Passivation Thickness Product Change Notice PDF 941 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
Flexible Solutions for Fast Edge Rate and Low Phase Noise Requirements Overview PDF 154 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clocks for Xilinx Ultrascale FPGAs Technical Brief PDF 256 KB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB