The 5V49EE504 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE504 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of four 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

Features

  • Four internal PLLs
  • Internal non-volatile EEPROM
  • Fast (400kHz) mode I2C serial interface
  • Input frequency range: 1 MHz to 200 MHz
  • Output frequency range: 4.9 kHz to 200 MHz
  • Reference crystal input with programmable linear load capacitance - Crystal frequency range: 8 MHz to 50 MHz
  • Two independently controlled VDDO (1.8V - 3.3V)
  • Each PLL has a 7-bit reference divider and a 12-bit feedback-divider
  • 8-bit output-divider blocks
  • Fractional division capability on one PLL
  • Two of the PLLs support spread spectrum generation capability
  • I/O Standards: - Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS - Inputs - 3.3 V LVTTL/ LVCMOS
  • Programmable slew rate control
  • Programmable loop bandwidth
  • Programmable output inversion to reduce bimodal jitter
  • Redundant clock inputs with auto and manual switchover options
  • Individual output enable/disable
  • Power-down mode
  • 3.3V core VDD
  • Available in VFQFPN package
  • -40 to +85 C Industrial Temp operation

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5V49EE504NLGI Active NLG24P1 VFQFPN 24 I Yes Tube
Availability
5V49EE504NLGI8 Active NLG24P1 VFQFPN 24 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
5V49EE504 Datasheet Datasheet PDF 326 KB
User Guides & Manuals
VersaClock3 Evaluation Board Setup Guide Manual - Eval Board PDF 147 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB
AN-831 The Crystal Load curve Application Note PDF 308 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 50 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PCNs & PDNs
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages Product Change Notice PDF 36 KB
PCN# : A1310-01 Changed of Material Sets Product Change Notice PDF 101 KB
PCN# : A1303-05 Stack Die Assembly with Interposer and Die Attach Material Change Product Change Notice PDF 275 KB
PCN# : A1301-08 Stack Die Assembly with Interposer Product Change Notice PDF 274 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
VersaClock III Eval Board Schematics Schematic PDF 80 KB
5V49EE504 Reference Schematic Misc PDF 21 KB
VersaClock3-ProgrammableClocks Product Brief PDF 1.61 MB
DesignTip-SpreadSpectrumClocking-VersaClock3 Product Brief PDF 199 KB

Software & Tools

Title Other Languages Type Format File Size Date
VersaClock 4.3 for Windows Vista Service Pack 2 64-bit Software ZIP 117.74 MB
VersaClock 4.3 for Windows XP Service Pack 2&3 32-bit Software ZIP 118.00 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 64-bit Software ZIP 117.74 MB
VersaClock 4.3 for Windows Vista Service Pack 2 32-bit Software ZIP 117.74 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 32-bit Software ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 64-bit Software ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 32-bit Software ZIP 118.54 MB
5V49EE504 IBIS Model Model - IBIS ZIP 288 KB