FemtoClock® LVDS Programmable Delay Line

The ICS854S296I-33 is a high performance LVDS Programmable Delay Line. The delay can vary from 2.2ns to 12.5ns in 10ps steps. The ICS854S296I-33 is characterized to operate from a 3.3V powersupply and is guaranteed over industrial temperature range. The delay of the device varies in discrete steps based on a control word. A 10-bit long control word sets the delay in 10ps increments. Also, the input pins IN and nIN default to an equivalent low state when left floating. The control register can accept CMOS or TTL level signals.

Features

  • One LVDS level output 
  • One differential clock input pair
  • Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML 
  • Maximum frequency: 1.2GHz
  • Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps
  • D[9:0] can accept LVPECL, LVCMOS or LVTTL levels
  • Full 3.3V supply voltages
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
854S296DKI-33LF Obsolete NLG32P1 VFQFPN 32 I Yes Tray Availability
854S296DKI-33LFT Obsolete NLG32P1 VFQFPN 32 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS854S296I-33 Datasheet Datasheet PDF 252 KB Jan 19, 2014
PCNs & PDNs
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB Nov 2, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
Other
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016