FemtoClock® VCXO-PLL Frequency Generator For Wireless Infrastructure Equipment

NOTICE - The following device(s) are recommended alternatives:

The 813078I is a member of the family of high performance clock solutions from IDT. The 813078I a PLL based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage attenuates the reference clock jitter by using an internal or external VCXO circuit. The internal VCXO requires the connection of an external inexpensive pullable crystal (XTAL) to the 813078I. This first PLL stage (VCXO PLL) uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The output of the first stage VCXO PLL is a stable and jitter-tolerant 30.72MHz reference input for the second PLL stage. The second PLL stage provides frequency translation by multiplying the output of the first stage up to 491.52MHz or 614.4MHz. The low phase noise characteristics of the VCXO-PLL clock signal is maintained by the internal FemtoClock® PLL, which requires no external components or complex programming. Two independently configurable frequency dividers translate the internal VCO signal to the desired output frequencies. All frequency translation ratios are set by device configuration pins. Supported input reference clock frequencies: 10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz, 61.44MHz, and 122.88MHz Supported output clock frequencies: 30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz, 153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz

Features

  • Nine outputs, organized in three independent output banks with differential LVPECL and single-ended outputs
  • One differential input clock can accept the following differential input levels: LVDS, LVPECL, LVHSTL
  • One single-ended clock input
  • Frequency generation optimized for wireless infrastructure
  • Attenuates the phase jitter of the input clock signal by using low-cost pullable fundamental mode crystal (XTAL)
  • Internal Femtoclock frequency multiplier stage eliminates the need for an expensive external high frequency VCXO
  • LVCMOS levels for all control I/O
  • RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal (12kHz to 20MHz): 1.1ps rms (typical)
  • RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal (12kHz to 20MHz): 0.97ps rms (typical)
  • VCXO PLL bandwidth can be optimized for jitter attenuation and reference frequency tracking using external loop filter components
  • PLL fast-lock control
  • PLL lock detect output
  • Absolute pull range is +/-50 ppm
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
813078BYILF Obsolete EDG64 TQFP 64 I Yes Tray Availability
813078BYILFT Obsolete EDG64 TQFP 64 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS813078I Datasheet Datasheet PDF 568 KB Jul 28, 2016
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-841 Pullable Crystal Selection and VCXO Tuning Application Note PDF 248 KB Sep 23, 2014
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-849 Loop Filter Component Selection for VCXO Based PLLs Application Note PDF 132 KB May 13, 2014
AN-848 VCXO - Crystal Selection Application Note PDF 138 KB May 13, 2014
AN-847 VCXO - Absolute Pull Range Application Note PDF 70 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 4, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 11, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-15-01 (R1) Quarter PDN for Declined Market Product Discontinuation Notice PDF 550 KB Mar 10, 2015
PDN# : CQ-15-01 Quarter PDN for Declined Market Product Discontinuation Notice PDF 547 KB Jan 22, 2015
PCN# : TB1405-01 New Carrier Tape and Quantity per Reel Product Change Notice PDF 788 KB Jul 6, 2014
Other
The IDT Communications Products Advantage Overview PDF 2.54 MB Feb 13, 2017
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
813078I IBIS Model - IBIS ZIP 76 KB Nov 4, 2009

News & Additional Resources