The F5390 is a 4-elements TRX half-duplex silicon IC designed using a 0.13 μm SiGe BiCMOS process for 39 GHz 5G phased-array applications. The core IC has 6-bit phase control and more than 35 dB gain control on each channel to achieve fine beam steering and gain compensation between radiating elements. In transmit mode, the chip has 25 dB gain and 13 to 14 dBm OP1dB. In the receive mode, it has 23 dB gain with a NF of 5.8 to 7.5 dB and an IP1dB of -27 dBm throughout the band. The core chip achieves an RMS phase error of 2 deg and RMS gain error of 0.6 dB in the receive mode. Moreover the IC keeps the phase variation less than +/-5 deg for a 10 dB gain back-off in both transmit and receive modes.
The chip operates at 2.1 to 2.5 V and features ESD protection on all pins. The core design includes standard SPI protocol that operates up 50 MHz with fast-beam switching, fast beam-state loading and fast four on-chip beam storage. The module has four external bias pins (5-bit DACs) to control external LNA/PA modules, temperature reporting and external biasing.
- 36-41 GHz operation
- 4 radiation elements
- Tx/Rx operation (Half duplex)
- 6-bit phase control
- 0.2 dB gain control (35 dB range)
- Advanced SPI with 4 state memory
- Fast beam steering (<30 ns)
- Hard-wired Tx/Rx switching (<30 ns)
- 6-bit chip address
- Integrated PTAT with external biasing
- Internal temperature sensor